Applicants claim the foreign priority benefits under 35 U.S.C. 119 of Japanese application 050307 filed on Feb. 25, 1991, which is wholly incorporated by reference herein.
The present invention pertains to information processing systems and, more particularly, to a power saving circuit that stops the processor clock signal or reduces its frequency during a processor idle state in order to decrease the power consumed by and the heat dissipated by the processor.
In a well known prior art processor, the contents of its internal registers are not lost if the clock signal to the processor is interrupted, and operations can be resumed from this halt state by simply restarting the clock signal to the processor. Such a processor may be called a "full-static processor." If the full-static processor uses CMOS logic, power consumption and the resulting heat generated can be greatly reduced if the clock signal to the processor is stopped while the processor is in an idle state. In addition, power consumption can also be reduced without stopping the clock signal to the processor if the frequency of the clock signal is decreased.
Japanese Published Unexamined Patent Application (PUPA) 62-169219 (U.S. Pat. No. 4,851,987) discloses an information processing system in which the clock signal to a processor is stopped in response to the execution of a program that determines whether the system is currently in a state where it waits for the completion of an operation of an input/output device or a key input from an operator. However, even though the system waits for the completion of an operation of an input/output device or a key input from an operator, the processor is not always in an idle state. This is particularly true in an information processing system that uses a multi-tasking operating system, wherein it is not unlikely that the processor is running a second task while waiting for the completion of an operation of an input/output device or a key input from an operator. Therefore, in the prior art device, there is a danger that the clock signal to the processor may be stopped while the processor is running a task.